In many digital data handling devices, multi-phase clocks are utilized to control the operation of the logic contained therein. In such apparatus it is sometimes desirable to stop or halt the operation of the multi-phase clocks and to resume clock sequencing at a later time. A problem prevalent among clocks which must be stopped at the end of a given sequence is the necessity of disabling the multi-phase clock drivers after the end of the last phase in the sequence and before the start of the first phase in the next sequence. Since the multi-phase clock controls the apparatus' operation, a relatively very short time period is available for this disabling operation. The result is generally either the early termination of the last phase in a sequence or a partial enabling of the first phase of the subsequent sequence.
This problem is especially prevalent in clock networks in which adjacent phases are not underlapped, that is, clock networks in which the first phase of one sequence follows immediately behind the last phase of the preceding clock sequence. There therefore exists no larger amount of time between the last phase of one sequence and the first phase of the next sequence than exists between two adjacent phases in one clock sequence. Since the time between adjacent phases in a multi-phase clock is the smallest time increment available in most of the digital apparatus, there exists no time larger than the smallest unit of time available in which the apparatus' digital logic is able to act to disable the multi-phase clock drivers.